Taiwan’s contract chip maker TSMC has revealed more details about its plans to develop new technological processes. In the coming years, we will see the 3nm N3 node and its upgraded version the N3E, as well as the 2nm N2.
The TSMC N3 technology will provide wider scalability over the N5. There is talk of a 1.7-fold increase in transistor density with a simultaneous increase in productivity (10-15%) and energy efficiency (25-30%). But these benefits come at the cost of multiples of complexity. EUV lithography will increase the number of layers and the number of steps required to obtain a finished plate.
“Risk production of the N3 is scheduled for 2021, with serial production starting in the second half of 2022,” said TSMC CEO Sisi Wei. “Therefore, we can expect the bulk of N3’s revenue to start coming in in the first quarter of 2023.”
“We also introduced the N3E node as an extension of our N3 family,” Wei continued. “N3E will feature an improved workflow window with improved performance, efficiencies and yields. The N3E is slated for mass production a year after the N3.”
The N2 process technology remains a mystery to this day. Previously, the chip maker publicly considered the possibility of using GAAFET (gate-all-around field-effect transistor) transistors, but did not confirm it conclusively. The TSMC chief limited himself to only approximate dates: “I can share with you that in our 2nm technology, density and performance will be most competitive in 2025,” Wei said.
a source:
Anandtech
